Super Deluxe Direct Conversion Transceiver

Features:

Operation:

To call a station, tune the receiver for 'Zero beat'. This would be the actual zero Hertz beat, so that the transmitter frequency will match that of the other station.

Once the station is zero beated, activate RIT by pushing the knob on the encoder. You can now tune +/- the transmit frequency to get the desired 600 Hz beat note.

When calling CQ, set the transmit frequency, then activate RIT and tune plus or minus 600 Hz so you can hear a station coming back to you.

Digital VFO:

In order to create a DDS VFO but using all through hole parts, a "hybred" approch had to be taken. The VFO consists of two main parts:

1), a low frequency DDS signal generated by a RISC processor running a simple DDS accumulator loop to address a 256 byte sine look up table, which is in turn drives a R-2R resistor D/A converter to produce a sine wave at about 219 kHz.

2), A 28 MHz VCO stablized by PLL. The 28 MHz R/C VCO is divided down to produce both the operating frequencies for the transciever and the frequency required by the PLL to match that of the DDS reference frequency at 219 kHz.

By changing the PLL reference frequency using the low frequency DDS signal, the VCO can be tuned over it's operating range. Operating the PLL at 219 kHz puts the sidebands well beyond the operating frequency. By using a frequency divided down from the VCO base frequency also helps to reduce PLL sidebands and reduce phase noise.

Interupting the accumulator loop running in the processor generating the DDS signal causes glitches in the output while it pauses to service the interupt. The PLL loop filter minimizes these glitches so long as they are kept very short. Therefore, a seperate processor is used for the control of the rig and to calculate the DDS phase word needed to output a specific frequency. Once the phase word is calculated, it is sent to the DDS processor via a very fast serial data connection.

The block diagram below illustrates the VFO design:

Frequency accuracy:

The contoller processor calculates the DDS phase word based on the desired final output frequency. Because that phase word is then divided to get the word needed to produce the low frequency reference signal and is then multiplied by the PLL and divided yet again to procuce the final output frequency, some round off errors creep in. Therefore, the actual output frequency and that shown on the display can be off as much as 500 Hz. Keep this in mind when operating near band edges.

The Receiver:

The Direct Conversion Receiver uses a 74HC4053 analog multiplexer as the mixer. Transformer coupling is used on both the input and output side of the mixer. 1/2 Vcc bias on the analog switches insures a large dynamic range and good rejection of AM signals which often plauge DC receivers. Other than the transmitter's Low Pass filter, the mixer input is not tuned which simplifies the input circuit and ensures a very wide tuning range.

The mixer output is followed by a high gain, differental input amplifier and then two stages of audio band pass filtering, centered at 600 Hz. These filters help to reduce QRM from other near-by stations. An additional stage of gain follows the band pass filters. A LM386 audio amp provides the final amount of gain and incorperates a AGC circuit to limit the output to a maximum of 1.2 volts peak to peak. This eliminates the need for a volume control and helps prevent very strong signals for blowing the headphones off your ears!

The Transmitter:

The transmitter uses three BS170 MOSFET transistors in parallel and are directly driven by the square wave output of the PLL divider. A DPDT slide switch is used to select which output from the divider is used. Power output is set by a variable voltage supply, which is also used to key the PA on and off.